The Cyclone EP1C20 Device
Figure 1–2. Nios Development Board Components
(J16)
40-pin header for
3.3 volt prototype
connector
(PROTO2)
(J12)
14-pin header for
5.0 volt prototype
connector
(PROTO1)
(J13)
20-pin header for
5.0 volt prototype
connector
(PROTO1)
(J11)
40-pin header for
5.0 volt prototype
connector
(PROTO1)
(L11)
(L11, L10)
Inductors
(L10)
(J25)
Debug mictor
connector
(J26 )
DC jack
The Cyclone
EP1C20 Device
1–4
Nios Development Board Reference Manual, Cyclone Edition
(J17)
(U36)
20-pin header for
SRAM
3.3 volt prototype
device
connector
(PROTO2)
(U35)
SRAM
device
(SW10)
Power-On Reset
button
(J19)
Serial port
(RJ1)
connector
RJ-45
connector
U60 is a Cyclone EP1C20F400C7 device in a 400-pin
package.
Table 1–1
Table 1–1. Cyclone EP1C20 Device Features
Logic Elements
M4K RAM blocks (128 X 36 bits)
Total RAM bits
PLLs
Maximum user I/O pins
(J15)
14-pin header for 3.3 volt
prototype connector
(PROTO2)
(Y2)
(J5)
Crystal
10-pin JTAG
Oscillator
header for
MAX device
(J4)
(SW9)
External
Safe Config
clock
Button
input
(J24)
10-pin JTAG
header for
(U4)
Cyclone
Ethernet
FPGA
PHY/MAC
device
lists the Cyclone device features.
(U60)
Cyclone
EP1C20F400C7
device
(SW3, SW2,
SW1, SW0)
User push-button
switches
(SW3)
(SW2)
(SW1)
(SW0)
(J28)
Serial flash
connector
(U59)
EPCS4
device
(SW8)
CPU reset
button
(CON3)
CompactFlash
connector header
(J27)
Serial port
connector
FineLine BGA
20,060
64
294,912
2
301
Altera Corporation
December 2004
®
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