Altera Cyclone V Reference Manual page 48

2–40
Table 2–28. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)
Board Reference
C7
B7
K1
J3
T2
L3
L8
DDR3 x16 (U27)
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M2
N8
M3
K3
K9
J7
K7
L2
E7
D3
E3
F7
F2
Cyclone V GT FPGA Development Board
Reference Manual
Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from
Schematic Cyclone V GT
Signal Name Pin Number
AD19
DDR3A_DQS_P1
AE19
DDR3A_DQS_N1
AN21
DDR3A_ODT
AP14
DDR3A_RASN
AJ22
DDR3A_RESETN
AN12
DDR3A_WEN
DDR3A_ZQ01
AK18
DDR3A_A0
AL18
DDR3A_A1
AM18
DDR3A_A2
AN18
DDR3A_A3
AH17
DDR3A_A4
AJ17
DDR3A_A5
AK17
DDR3A_A6
AL17
DDR3A_A7
AH16
DDR3A_A8
AJ16
DDR3A_A9
AL16
DDR3A_A10
AM16
DDR3A_A11
AM13
DDR3A_A12
AN13
DDR3A_A13
AN16
DDR3A_BA0
AN17
DDR3A_BA1
AP17
DDR3A_BA2
AP15
DDR3A_CASN
AP26
DDR3A_CKE
AA18
DDR3A_CLK_P
AA17
DDR3A_CLK_N
AA16
DDR3A_CSN
AM28
DDR3A_DM2
AL27
DDR3A_DM3
AP27
DDR3A_DQ16
AN27
DDR3A_DQ17
AK22
DDR3A_DQ18
I/O Standard
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
— 1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Chapter 2: Board Components
Memory
Description
Data strobe P byte lane 1
Data strobe N byte lane 1
On-die termination enable
Row address select
Reset
Write enable
ZQ impedance calibration
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Bank address bus
Bank address bus
Bank address bus
Row address select
Column address select
Differential output clock
Differential output clock
Chip select
Write mask byte lane
Write mask byte lane
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
August 2017 Altera Corporation