Omron DRT2 Series Operation Manual page 163

Analog Input Terminals
Top/Valley Detection
Timing Flags + Generic
Status Flags (Instance
151)
Analog Status Flags +
Generic Status Flags
(Instance 164)
Analog Data 1 + Top/Valley
Detection Timing Flags
(Instance174)
146
This data pattern consists of the Top/Valley Detection Timing Flags followed
by Generic Status Flags and is allocated in the Master using the following
data format, shown by byte (3 bytes).
Bit 7 Bit 6
+0 0 0
+1 0 0
+2 0 0
The following format is used when this data pattern is allocated, starting from
the rightmost byte of the Master
Word 15
+0
+1
This data pattern consists of Analog Status Flags followed by Generic Status
Flags and is allocated in the Master using the following data format, shown by
byte (5 bytes).
Bit 7 Bit 6
+0 BD0 T_ST0 V_ST0
+1 BD1 T_ST1 V_ST1
+2 BD2 T_ST2 V_ST2
+3 BD3 T_ST3 V_ST3
+4 0 0
The following format is used when this data pattern is allocated, starting from
the rightmost byte of the Master
Word 15
+0
+1
+2
This data pattern consists of Analog Data 1 followed by the Top/Valley Detec-
tion Timing Flags and is allocated in the Master using the following data for-
mat (10 bytes).
Bit 7 Bit 6
+0
+1
+2
+3
+4
+5
+6
+7
+8 0 0
+9 0 0
Bit 5 Bit 4 Bit 3
0 0 V_ST3
0 0 T_ST3
MRF CCW RHW
.
8 7
Top Detection
Timing Flags
Bit 5 Bit 4 Bit 3 Bit 2
HH H
HH H
HH H
HH H
MRF CCW RHW NPW
.
8
For Input 1
For Input 3
Bit 5 Bit 4 Bit 3
Analog Data 1 for Input 0
Analog Data 1 for Input 1
Analog Data 1 for Input 2
Analog Data 1 for Input 3
0 0 V_ST3
0 0 T_ST3
Section 7-3
Bit 2 Bit 1 Bit 0
V_ST2 V_ST1 V_ST0
T_ST2 T_ST1 T_ST0
NPW 0
Valley Detection
Timing Flags
Generic Status Flags
Bit 1 Bit 0
PS0 LL L Input
PS1 LL L Input
PS2 LL L Input
PS3 LL L Input
0 0
7
For Input 0
For Input 2
Generic Status Flags
Bit 2 Bit 1 Bit 0
V_ST2 V_ST1 V_ST0
T_ST2 T_ST1 T_ST0
0
0
0
1
2
3
0