HP MC68040 User Manual page 656

Chapter 18: Connecting the Emulator to a Target System
Verifying Operation Of The Emulator In Your Target System
If there are many cycles in the trace list before the processor stalled, use a different
method of triggering. There are a number of different approaches that can be used.
The most direct method is to trigger on a condition of TIP low and TA high for a
period of time greater than the length of a memory cycle. Another method is to
determine if the system always stops at the same address. This address can then be
used as the trigger. One drawback to this method is that you may have to probe a
large number of signals to get a unique address.
A better way would be to use the emulation-bus analyzer to generate a trigger.
Unfortunately, because the cycle never finishes, the emulation-bus analyzer will not
capture this address, so something preceding this event must be used as the trigger.
Examine the trace list to find a unique event to use as the trigger. Once you have
specified the trigger, you need to configure the emulator to drive the trigger out.
The real trick to crosstriggering is to correlate the trigger event to the captured data.
In this type of measurement, the correlation is easy because the signals of interest
stop transitioning shortly after the trigger occurs.
tg addr=00badad00
tp c
tgout trig2
bnct -r trig2
t
Once you have a trace of the offending cycle, verify that TA is present for a valid
rising clock edge, taking into account a wait state if running faster than 25 MHz. If
TA looks reasonably correct, verify the setup and hold specifications. If TA occurs
but on an invalid clock edge, you may need to make modifications to the target
system to ensure that there is at least one wait state in target cycles. If TA is not
asserted at all, it could be an indication that the target system missed the TS. Set up
your oscilloscope or logic analyzer to make a measurement on your cycle start
circuitry to determine why the target system did not respond to the cycle.
If the cycle where processing stops is part of a burst cycle, as indicated by the line
access type in the status display, there are several things to check.
w>es
w>
A burst cycle is shown below. The main characteristic of a burst cycle is that there
are four data transfers as part of one cycle. The processor puts out an address and
asserts TS only once during the cycle. A burst request is indicated by the SIZx
signals. The target memory system can inhibit the burst cycle by asserting the TBI
signal. If the cycle is inhibited, the timing becomes just like a normal cycle. If the
cycle is not inhibited, once TS has been asserted, the process starts sampling TA for
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M68040--CPU in wait state; 000000000@sd line read