Siemens SINUMERIK 840D sl Function Manual page 245

● OB40_INT is the maximum permissible time to initiate the interrupt on the NCK side up to
execution of the PROFIsafe software and a ready signal to the NCK. The time is mainly
determined by the run time (propagation time) of the F-driver implementation on the PLC
side and the PLC user program to be run-through in the OB40 context. These times typically
lie in the vicinity of a few milliseconds.
● The error response for system errors (see Alarm 27355) and F_DP communication errors:
Sequence number and CRC (see Alarms 27350 / 27351: SN and CRC) realized in the
F_DP clock cycle in which the error is identified.
● The error response for F_DP communication error TIMEOUT (see Alarms 27350 and
27351: TO) is realized in the F_DP clock cycle in which the parameterized timeout time
(FSDP: MD13335 $MN_SAFE_SDP_TIMEOUT, FRDP: MD13345
$MN_SAFE_RDP_TIMEOUT) is exceeded.
● The specified maximum times are theoretical values; it is extremely improbable that they
actually occur in practice.
Reason:
● It is improbable that the run time of the PLC-F driver is delayed - in the OB40 context - by
the maximum time of 500 ms. The reason for this is that the interrupting organizational
blocks (OB8x) only have such long run times in extremely few cases.
● For the theoretical value, it would be necessary that two consecutive runs of the PLC-F_DP
layer in the OB40 context are delayed by the permitted maximum of 500 ms - this is
extremely improbable.
● The maximum time of 150 ms for the user program is not reached in any of the applications
relevant in practice.
PLC processing times
Times: T(FRDP - DB18)
Formula
Maximum times
Typical times
1)
Times: T(DB18 - FSDP)
Formula
Maximum times
Typical times
1)
Times:T(FRDP → FSDP)
Formula
Maximum times
Typical times
1)
F_DP clock cycle = n * IPO; with n = 1, 2, 3, ...
Typical times: IPO = 8 ms; n = 10 => F_DP clock cycle = 80 ms; OB1 = 30 ms
1)
Safety Integrated
Function Manual, 12/2017, 6FC5397-4BP40-6BA1
8.4 Safety-related CPU-CPU communication (F_DP communication)
2 * F_DP clock cycle + 1 * OB1
2 * 500 ms + 1 * 150 ms
2 * 80 ms + 1 * 30 ms
2 * F_DP clock cycle + 1 * OB1
2 * 500 ms + 1 * 150 ms
2 * 80 ms + 1 * 30 ms
4 * F_DP clock cycle + 2 * OB1
4 * 500 ms + 2 * 150 ms
4 * 80 ms + 2 * 30 ms
Connecting sensors and actuators
1150 ms
10 ms
1150 ms
190 ms
2300 ms
30 ms
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