Register Communication; Table 34: Setup Of The Process Image For Register Communication; Table 35: Control Byte C - WAGO I/O-SYSTEM 750 Manual

60 Process Image
6.3.3

Register Communication

Some I/O modules of the 750 series offer a protocol subsequently referred to as
"register communication" for the configuration. Register communication provides
read and/or write access to up to 64 data words designated as "registers" of the
respective I/O module. This protocol allows, for example, data exchange between
the 750-644 I/O module and a PLC application.
Register communication of the 750-644 I/O module is not a permanent part of the
process image, but may be mapped as required. If mapped, the process image is
only available for register communication, i.e. no other process data or Mailbox
data can be transmitted.
If bit 7 is set in the control byte of the process image of the outputs, it is viewed as
a request to the 750-644 I/O module to map register communication. The 750-644
I/O module responds to the request by setting bit 7 in the status byte. Register
communication is thus considered mapped.
Revoking Mailbox and process data validity
During register communication, the Mailbox and process data is no longer valid!
The register communication protocol uses bytes 0, 2 and 3 of the process image.
All other bytes are not valid in this state.

Table 34: Setup of the process image for register communication

Byte
0
1
2
3
4 ... 47 2 ... 23
If register communication is enabled, the control/status byte must be interpreted
otherwise.
For register communication, the control byte is occupied as follows:

Table 35: Control byte C

Bit 7
1
REG_NO
RW
For register communication, the status byte is occupied as follows:
Word Input process image
0 Control byte C
Internal byte
1 D0
D1
Invalid
Bit 6 Bit 5
RW
Register number (e.g. 56 or 57)
0: Read access
1: Write access
750-644 Bluetooth
Control byte C
Bit 4 Bit 3
REG_NO
Version 2.0.0, valid from FW/HW Version 03/03
WAGO-I/O-SYSTEM 750
®
RF-Transceiver
Output process image
Status byte S
Internal byte
D0
D1
Invalid
Bit 2 Bit 1
Manual
Bit 0