Bus Matrix - Toshiba TXZ+ TMPM4KLFYAUG Reference Manual

TXZ+ Family
TMPM4K Group(2)
Clock Control and Operation Mode

2.2. Bus Matrix

TMPM4K Group(2) contains the CPU Core of the main master and sub masters. The sub masters include DMA
controller (DMAC) and NBDIF.
Main masters connect to slave ports (S0 to S3) of Bus Matrix. In the bus matrix, master ports (M0 to M9) connect
to peripheral functions via connections described as (○) or (●) in the following figure. (●) shows a connection to a
mirror area.
Sub-masters connect to slave ports (SS0 to SS2) of Bus Matrix. In the bus matrix, sub ports (SM0 to M8) connect
to peripheral functions via connections described as (○) or (●) in the following figure.
While multiple slaves are connected to the same bus master line in the Bus Matrix, if multiple slave accesses are
generated at the same time, a priority is given to access from a master with the smallest slave number.
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