Xilinx 7 Series User Manual page 45

Overflow and Underflow Logic
The discussion of overflow and underflow below applies to sequential accumulators
(MACC or Adder-Accumulator) implemented in a single DSP48E1 slice. The accumulator
should have at least one guard bit. When the pattern detector is set to detect a pattern equal
to 00000...0 with a mask of 0011111 ...1 (default settings), the DSP48E1 slice flags
overflow beyond 00111 ... 1 or underflow beyond 11000... 0. The
USE_PATTERN_DETECT attribute is set to PATDET to enable the use of the pattern detect
logic. This overflow/underflow implementation uses a redundant sign bit and reduces the
output bit width to 47 bits.
X-Ref Target - Figure 2-18
By setting the mask to other values like 0000111 ...1, the bit value P[N] at which overflow
is detected can be changed. This logic supports saturation to a positive number of 2
and a negative number of 2
field.
To check overflow/underflow condition for N = 2, the following example is used:
•
•
•
See
X-Ref Target - Figure 2-19
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
PATTERNDETECTPAST
PATTTERNBDETECT
PATTTERNDETECT
PATTERNBDETECTPAST
PATTERNBDETECT
PATTERNDETECT
Notes:
1. Denotes an internal signal.
Figure 2-18: Overflow/Underflow Logic in Pattern Detect
N
in two's complement where N is the number of 1s in the mask
Mask is set to 0...11.
The (N) LSB bits are not considered for the comparison.
For N = 2, the legal values (patterns) are 2
Figure 2-19 and Figure 2-20
x x x
PD Caused by Overflow
Overflow
Figure 2-19: Overflow Condition in the Pattern Detector
www.xilinx.com
Simplified DSP48E1 Slice Operation
(1)
(1)
PATTERN = 48'b00000000...
MASK = 48'b00111111...
2 2
-1 to –2 or 3 to –4.
for overflow and underflow examples, respectively.
x x 0 .. 0000 0 .. 0001
Overflow
Underflow
UG369_c1_18_051209
N
– 1
0 .. 0010 0 .. 0011 0 .. 0100
High to Low
UG369_c1_19_051209
Send Feedback
45