Xilinx 7 Series User Manual page 34

Chapter 2: DSP48E1 Description and Specifics
Table
function at the outputs of the three multiplexers (X, Y, and Z multiplexers). The
multiplexer outputs supply three operands to the following adder/subtracter. Not all
possible combinations for the multiplexer select bits are allowed. Some are marked in the
tables as "illegal selection" and give undefined results. If the multiplier output is selected,
then both the X and Y multiplexers are used to supply the multiplier partial products to the
adder/subtracter.
Table 2-7: OPMODE Control Bits Select X Multiplexer Outputs
Z
OPMODE[6:4] OPMODE[3:2]
xxx
xxx
xxx
xxx
Table 2-8: OPMODE Control Bits Select Y Multiplexer Outputs
Z
OPMODE[6:4] OPMODE[3:2]
xxx
xxx
xxx
xxx
Table 2-9: OPMODE Control Bits Select Z Multiplexer Outputs
Z
OPMODE[6:4] OPMODE[3:2]
000
001
010
011
100
101
110
111
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2-7, Table 2-8, and Table 2-9
Y X
OPMODE[1:0]
xx
00
01 01
xx
10
xx
11
Y X
OPMODE[1:0]
xx
00
01 01
xx
10
xx
11
Y X
OPMODE[1:0]
xx xx
xx xx
xx xx
xx xx
10 00
xx xx
xx xx
xx xx
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list the possible values of OPMODE and the resulting
X
Multiplexer Output
0 Default
M Must select with
OPMODE[3:2] = 01
P Must select with PREG = 1
A:B 48 bits wide
Y
Multiplexer Output
0 Default
M Must select with
OPMODE[1:0] = 01
Used mainly for logic unit
48'FFFFFFFFFFFF
bitwise operations on the X and
Z multiplexers
C
Z
Multiplexer Output
0 Default
PCIN
P Must select with PREG = 1
C
P Use for MACC extend only.
Must select with PREG = 1
17-bit Shift (PCIN)
17-bit Shift (P) Must select with PREG = 1
xx Illegal selection
Notes
Notes
Notes
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018