Memory-Mapped I/O Register Application - Xilinx 7 Series User Manual

Chapter 3: DSP48E1 Design Considerations
X-Ref Target - Figure 3-6
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Memory-Mapped I/O Register Application

To use DSP48E1 slices as memory-mapped I/O registers, you must broadcast the write
data bus feeding to all the DSP48E1 slices to be used in this fashion. To have random read
access, a wide multiplexer is needed. Additional DSP48E1 slices can be configured as a
wide bus multiplexer to help reduce routing congestion. An address decoder should be
implemented in fabric logic to control individual PREG CEs to load the appropriate DSP
output register from the write data bus.
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Figure 3-6: 8-Tap Even Symmetric Systolic FIR
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UG479_c2_06_072210
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018