Adder Tree Versus Adder Cascade; Adder Tree - Xilinx 7 Series User Manual

Chapter 3: DSP48E1 Design Considerations

Adder Tree Versus Adder Cascade

Adder Tree

In typical direct form FIR filters, an input stream of samples is presented to one input of the
multipliers in the DSP48E1 slices. The coefficients supply the other input to the multipliers.
An adder tree is used to combine the outputs from many multipliers as shown in
Figure
X-Ref Target - Figure 3-1
h7(n)
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18
h6(n)
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X(n-4)
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Z -2
h5(n)
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h4(n)
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X(n-2)
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Z -2
h3(n)
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h2(n)
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X(n)
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Z -2
h1(n)
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h0(n)
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X(n)
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48
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3-1.
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48
48
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Figure 3-1: Traditional FIR Filter Adder Tree
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The final stages of the post
addition in logic are the
performance bottleneck that
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consume more power.
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
y(n-6)
UG479_c2_01_072210