Revision History - Xilinx 7 Series User Manual

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Revision History

The following table shows the revision history for this document.
Date Version
03/01/2011 1.0
03/28/2011 1.1
10/18/2011 1.2
01/30/2012 1.3
10/02/2012 1.4
04/03/2013 1.5
7 Series DSP48E1 User Guide
Initial Xilinx release.
Added Chapter 1, Overview.
Updated DSP48E1 Slice Features. In
XC7K355T, XC7K420T, and XC7K480T.
Added Stacked Silicon Interconnect.
Updated DSP48E1 column range and upper limit of DSP slices in
Interconnect. Added Artix-7 and Virtex-7 families to
Added Memory-Mapped I/O Register
Removed top performance value of 600 MHz throughout. In
XC7A15, XC7A30T, and XC7A50T, and updated number of DSP48E1 slices per column
for XC7K420T and XC7VX550T. Updated lower limit for number of DSP48E1 columns
and DSP slices in DSP48E1 Tile and
Updated Device Resources.
Updated last sentence in first paragraph of
removed XC7A350T and XC7V1500T, and added XC7VH580T and XC7VH870T.
Updated link for UG687 in
and Table 2-2. Updated first and last paragraphs in
Generations.
www.xilinx.com
Revision
Table 2-1, removed XC7K30T and added
Table
Application.
Interconnect.
DSP48E1 Tile and
Additional Documentation
Features Relative to Prior
DSP48E1 Tile and
2-1, including table notes.
Table 2-1, removed XC7A8,
Interconnect. In Table
Resources. Updated Table 2-1
UG479 (v1.10) March 27, 2018
2-1,