Features Relative To Prior Generations; Device Resources - Xilinx 7 Series User Manual

Chapter 1: Overview
•
•
•
•

Features Relative to Prior Generations

The 7 series FPGA DSP48E1 slice is functionally equivalent and fully compatible with the
Virtex®-6 FPGA DSP48E1 slice, and a superset of the Virtex-5 FPGA DSP48E slice
The 7 series FPGA DSP48E1 slice offers more capability than the DSP48A1 slice of the
Spartan®-6 FPGA family with these differences:
•
•
Virtex-6 family DSP designs migrate directly to the DSP resources of the 7 series. Migration
of designs with cascaded DSP slices should consider the number of DSP slices per column.
Spartan-6 family DSP designs can be converted to the 7 series, but designers should
examine how to take advantage of the greater capability of the DSP48E1 slice. See UG429,
7 Series FPGAs Migration User Guide for more information.

Device Resources

The DSP resources are optimized and scalable across all the 7 series families, providing a
common architecture that improves implementation efficiency, IP implementation, and
design migration. The number of DSP48E1 slices and the ratio between DSP and other
device resources differentiates the 7 series families. Migration between the 7 series families
does not require any design changes for the DSP48E1.
See
FPGAs Overview
10
Send Feedback
Single-instruction-multiple-data (SIMD) arithmetic unit:
• Dual 24-bit or quad 12-bit add/subtract/accumulate
Optional logic unit:
• Can generate any one of ten different logic functions of the two operands
Pattern detector:
• Convergent or symmetric rounding
• 96-bit-wide logic functions when used in conjunction with the logic unit
Advanced features:
• Optional pipelining and dedicated buses for cascading
Wider functionality in DSP48E1 than DSP48A1:
• Multiplier width is improved from 18 x 18 in the Spartan-6 family to 25 x 18 in the
7 series
• The A register width is improved from 18 bits in the Spartan-6 family to 30 bits in
the 7 series:
- A and B registers can be concatenated in the 7 series
- The A register feeds the pre-adder in the 7 series instead of the B register
• Cascading capability on both pipeline paths for larger multipliers and larger
post-adders
Unique features in DSP48E1 over DSP48A1:
• Arithmetic logic unit (ALU)
• SIMD mode
• Pattern detector
• 17-bit shifter
Table 2-1 for the available DSP48E1 resources for the 7 series FPGAs. Refer to 7 Series
[Ref 2] for the most up-to-date information on all the 7 series FPGAs.
www.xilinx.com
[Ref 1].
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018