Xilinx 7 Series User Manual page 18

Chapter 2: DSP48E1 Description and Specifics
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Each DSP48E1 slice has a two-input multiplier followed by multiplexers and a three-input
adder/subtracter/accumulator. The DSP48E1 multiplier has asymmetric inputs and
accepts an 18-bit two's complement operand and a 25-bit two's complement operand. The
multiplier stage produces a 43-bit two's complement result in the form of two partial
products. These partial products are sign-extended to 48 bits in the X multiplexer and
Y multiplexer and fed into three-input adder for final summation. This results in a 43-bit
multiplication output, which has been sign-extended to 48 bits. Therefore, when the
multiplier is used, the adder effectively becomes a two-input adder.
The second stage adder/subtracter accepts three 48-bit, two's complement operands and
produces a 48-bit, two's complement result when the multiplier is bypassed by setting
USE_MULT attribute to NONE and with the appropriate OPMODE setting. In SIMD
mode, the 48-bit adder/subtracter also supports dual 24-bit or quad 12-bit SIMD
arithmetic operations with CARRYOUT bits. In this configuration, bitwise logic operations
on two 48-bit binary numbers are also supported with dynamic ALUMODE control
signals.
Higher level DSP functions are supported by cascading individual DSP48E1 slices in a
DSP48E1 column. Two datapaths (ACOUT and BCOUT) and the DSP48E1 slice outputs
(PCOUT, MULTSIGNOUT, and CARRYCASCOUT) provide the cascade capability. The
ability to cascade datapaths is useful in filter designs. For example, a Finite Impulse
Response (FIR) filter design can use the cascading inputs to arrange a series of input data
samples and the cascading outputs to arrange a series of partial output results. The ability
to cascade provides a high-performance and low-power implementation of DSP filter
functions because the general routing in the fabric is not used.
The C input port allows the formation of many 3-input mathematical functions, such as
3-input addition or 2-input multiplication with an addition. One subset of this function is
the valuable support of symmetrically rounding a multiplication toward zero or toward
infinity. The C input together with the pattern detector also supports convergent rounding.
For multi-precision arithmetic, the DSP48E1 slice provides a right wire shift by 17. Thus, a
partial product from one DSP48E1 slice can be right justified and added to the next partial
product computed in an adjacent DSP48E1 slice. Using this technique, the DSP48E1 slices
can be used to build bigger multipliers.
Programmable pipelining of input operands, intermediate products, and accumulator
outputs enhances throughput. The 48-bit internal bus (PCOUT/PCIN) allows for
aggregation of DSP slices in a single column. Fabric logic is needed when spanning
multiple columns.
The pattern detector at the output of the DSP48E1 slice provides support for convergent
rounding, overflow/underflow, block floating point, and support for accumulator
terminal count (counter auto reset). The pattern detector can detect if the output of the
DSP48E1 slice matches a pattern, as qualified by a mask.
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• Cascaded CARRYCASCOUT and MULTSIGNOUT allows for MACC extensions
up to 96 bits
Optional input, pipeline, and output/accumulate registers
Optional control registers for control signals (OPMODE, ALUMODE, and
CARRYINSEL)
Independent clock enable and resets for greater flexibility, with reset having priority.
To save power when the first stage multiplier is not being used, the USE_MULT
attribute allows the customer to gate off internal multiplier logic.
www.xilinx.com 7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018