Simplified Dsp48E1 Slice Operation - Xilinx 7 Series User Manual

Chapter 2: DSP48E1 Description and Specifics
Table 2-2: DSP48E1 Port Descriptions (Cont'd)
Name Direction
RSTINMODE
RSTM
RSTP
UNDERFLOW
Notes:
1. When these data ports are not in use and to reduce leakage power dissipation, the data port input signals must be tied High, the port
input register must be selected, and the CE and RST input control signals must be tied Low. An example of unused C port
recommended settings would be setting C[47:0] = all ones, CREG = 1, CEC = 0, and RSTC = 0.
2. These signals are dedicated routing paths internal to the DSP48E1 column. They are not accessible via fabric routing resources.
3. All signals are active High.

Simplified DSP48E1 Slice Operation

The math portion of the DSP48E1 slice consists of a 25-bit pre-adder, a 25-bit by 18-bit two's
complement multiplier followed by three 48-bit datapath multiplexers (with outputs X, Y,
and Z). This is followed by a three-input adder/subtracter or two-input logic unit (see
Figure
The data and control inputs to the DSP48E1 slice feed the arithmetic and logic stages. The
A and B data inputs can optionally be registered one or two times to assist the construction
of different, highly pipelined, DSP application solutions. The D path and the AD path can
each be registered once. The other data inputs and the control inputs can be optionally
registered once. Maximum frequency operation as specified in the data sheet is achieved
by using pipeline registers. More detailed timing information is available in
DSP48E1 Design
In its most basic form, the output of the adder/subtracter/logic unit is a function of its
inputs. The inputs are driven by the upstream multiplexers, carry select logic, and
multiplier array.
Equation 2-1
CIN, X multiplexer output, and Y multiplexer output are always added together. This
combined result can be selectively added to or subtracted from the Z multiplexer output.
The second option is obtained by setting the ALUMODE to 0001.
A typical use of the slice is where A and B inputs are multiplied and the result is added to
or subtracted from the C register. More detailed operations based on control and data
inputs are described in later sections. Selecting the multiplier function consumes both
X and Y multiplexer outputs to feed the adder. The two 43-bit partial products from the
multiplier are sign extended to 48 bits before being sent to the adder/subtracter.
When not using the first stage multiplier, the 48-bit, dual input, bitwise logic function
implements AND, OR, NOT, NAND, NOR, XOR, and XNOR. The inputs to these
functions are A:B, C, P, or PCIN selected through the X and Z multiplexers, with the
Y multiplexer selecting either all 1s or all 0s depending on logic operation.
The output of the adder/subtracter or logic unit feeds the pattern detector logic. The
pattern detector allows the DSP48E1 slice to support Convergent Rounding, Counter
Autoreset when a count value has been reached, and Overflow/Underflow/Saturation in
24
Send Feedback
Bit Width
In 1 Reset for the INMODE (control input) registers.
In 1 Reset for the M (pipeline) register.
In 1 Reset for the P (output) register.
Out 1 Underflow indicator when used with the appropriate setting of the
pattern detector.
2-5). When using two-input logic unit, the multiplier cannot be used.
Considerations.
summarizes the combination of X, Y, Z, and CIN by the adder/subtracter. The
Adder/Sub Out = (Z ± (X + Y + CIN)) or (-Z + (X + Y + CIN) –1)
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Description
Equation 2-1
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
Chapter 3,