Xilinx 7 Series User Manual page 22

Chapter 2: DSP48E1 Description and Specifics
Table 2-2: DSP48E1 Port Descriptions
Name Direction
(1)
A
(2)
ACIN
(2)
ACOUT
ALUMODE
(1)
B
(2)
BCIN
(2)
BCOUT
(1)
C
(2)
CARRYCASCIN
(2)
CARRYCASCOUT
CARRYIN
CARRYINSEL
CARRYOUT
CEA1
CEA2
CEAD
CEALUMODE
CEB1
CEB2
CEC
CECARRYIN
22
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Bit Width
In 30 A[24:0] is the A input of the multiplier or the pre-adder. A[29:0] are
the most significant bits (MSBs) of the A:B concatenated input to the
second-stage adder/subtracter or logic function.
In 30 Cascaded data input from ACOUT of previous DSP48E1 slice
(muxed with A).
Out 30 Cascaded data output to ACIN of next DSP48E1 slice.
In 4 Controls the selection of the logic function in the DSP48E1 slice (see
Table 2-13, page
In 18 The B input of the multiplier. B[17:0] are the least significant bits
(LSBs) of the A:B concatenated input to the second-stage
adder/subtracter or logic function.
In 18 Cascaded data input from BCOUT of previous DSP48E1 slice (muxed
with B).
Out 18 Cascaded data output to BCIN of next DSP48E1 slice.
In 48 Data input to the second-stage adder/subtracter, pattern detector, or
logic function.
In 1 Cascaded carry input from CARRYCASCOUT of previous DSP48E1
slice.
Out 1 Cascaded carry output to CARRYCASCIN of next DSP48E1 slice.
This signal is internally fed back into the CARRYINSEL multiplexer
input of the same DSP48E1 slice.
In 1 Carry input from the FPGA logic.
In 3 Selects the carry source (see
Out 4 4-bit carry output from each 12-bit field of the
accumulate/adder/logic unit. Normal 48-bit operation uses only
CARRYOUT3. SIMD operation can use four carry out bits
(CARRYOUT[3:0]).
In 1 Clock enable for the first A (input) register. A1 is only used if
AREG = 2 or INMODE[0]= 1.
In 1 Clock enable for the second A (input) register. A2 is only used if
AREG = 1 or 2 and INMODE[0]=0.
In 1 Clock enable for the pre-adder output AD pipeline register.
In 1 Clock enable for ALUMODE (control inputs) registers.
In 1 Clock enable for the first B (input) register. B1 is only used if
BREG = 2 or INMODE[4] = 1.
In 1 Clock enable for the second B (input) register. B2 is only used if
BREG = 1 or 2 and INMODE[4]=0.
In 1 Clock enable for the C (input) register.
In 1 Clock enable for the CARRYIN (input from FPGA logic) register.
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Description
42).
Table 2-11).
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018