Adder Cascade - Xilinx 7 Series User Manual

Chapter 3: DSP48E1 Design Considerations
X-Ref Target - Figure 3-3
The 3:1 adder shown in
Depending on the number of inputs to be added, a 5:3 or a 6:3 compressor is also built in
fabric logic using multiple 5LUTs or 6LUTs. The serial combination of 6:3 compressor,
along with two DSP48E1 slices, adds six operands together to produce one output, as
shown in
shift of the Y and Z buses should be tied to zero. The last DSP48E1 slice uses 2-deep A:B
input registers to align (pipeline matching) the X bus to the output of the first DSP48E1
slice. Multiple levels of 6:3 compressors can be used to expand the number of input buses.
X-Ref Target - Figure 3-4
The logic equations for the X, Y, and Z buses in
The compressor elements and cascade adder can be arranged like a tree to build larger
adders. The last add stage should be implemented in the DSP48E1 slice. Pipeline registers
should be added as needed to meet timing requirements of the design. These adders can
have higher area and/or power than the adder cascade.

Adder Cascade

The adder cascade implementation accomplishes the post addition process with minimal
silicon resources by using the cascade path within the DSP48E1 slice. This involves
computing the additive result incrementally, utilizing a cascaded approach as illustrated in
Figure
50
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A
46
3:2
B
Compressor
46
C
46
Figure 3-3
Figure 3-4. The LSB bits of the first DSP48E1 slice that are left open due to left
A
45
6:3
Compressor
F
45
X(n) = A(n) XOR B(n) XOR C(n) XOR D(n) XOR E(n) XOR F(n)
Y(n) = A(n)B(n) XOR A(n)C(n) XOR A(n)D(n) XOR A(n)E(n)
XOR A(n)F(n) XOR B(n)C(n) XOR B(n)D(n) XOR B(n)E(n)
XOR B(n)F(n) XOR C(n)D(n) XOR C(n)E(n) XOR C(n)F(n)
XOR D(n)E(n) XOR D(n)F(n) XOR E(n)F(n)
Z(n) = A(n)B(n)C(n)D(n) OR A(n)B(n)C(n)E(n) OR A(n)B(n)C(n)F(n)
OR A(n)B(n)D(n)E(n) OR A(n)B(n)D(n)F(n) OR A(n)B(n)E(n)F(n)
OR A(n)C(n)D(n)E(n) OR A(n)C(n)D(n)F(n) OR A(n)C(n)E(n)F(n)
OR A(n)D(n)E(n)F(n) OR B(n)C(n)D(n)E(n) OR B(n)C(n)D(n)F(n)
OR B(n)C(n)E(n)F(n) OR B(n)D(n)E(n)F(n) OR C(n)D(n)E(n)F(n)
3-5.
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ABUS
BBUS
Left Shift By 1
Figure 3-3: Three-Input Adder
is used as a building block for larger adder trees.
X
Y
Left Shift By 1
Z
Left Shift By 2
Figure 3-4: Six-Input Adder
Figure 3-4
2-Input
SUM
Cascade
48
Adder
UG479_c2_03_072210
DSP48E1
Slice
DSP48E1
Slice
UG479_c2_04_072210
are listed here:
Equation 3-1
Equation 3-2
Equation 3-3
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
SUM
48