Dsp48E1 Slice Features - Xilinx 7 Series User Manual

Chapter 2: DSP48E1 Description and Specifics
X-Ref Target - Figure 2-1
BCOUT* ACOUT*
18
B
Dual B Register
B
18
A
30
A
Dual A, D,
and Pre-adder
30
D 25
C
4
INMODE 5
CARRYIN
OPMODE
CARRYINSEL
BCIN* ACIN*
*These signals are dedicated routing paths internal to the DSP48E1 column. They are not accessible via fabric routing resources.

DSP48E1 Slice Features

This section describes the 7 series FPGA DSP48E1 slice features.
The DSP slice consists of a multiplier followed by an accumulator. At least three pipeline
registers are required for both multiply and multiply-accumulate operations to run at full
speed. The multiply operation in the first stage generates two partial products that need to
be added together in the second stage.
When only one or two registers exist in the multiplier design, the M register should always
be used to save power and improve performance.
Add/Sub and Logic Unit operations require at least two pipeline registers (input, output)
to run at full speed.
The cascade capabilities of the DSP slice are extremely efficient at implementing high-
speed pipelined filters built on the adder cascades instead of adder trees.
Multiplexers are controlled with dynamic control signals, such as OPMODE, ALUMODE,
and CARRYINSEL, enabling a great deal of flexibility. Designs using registers and
dynamic opmodes are better equipped to take advantage of the DSP slice capabilities than
combinatorial multiplies.
In general, the DSP slice supports both sequential and cascaded operations due to the
dynamic OPMODE and cascade capabilities. Fast Fourier Transforms (FFTs), floating
point, computation (multiply, add/sub, divide), counters, and large bus multiplexers are
some applications of the DSP slice.
Additional capabilities of the DSP slice include synchronous resets and clock enables, dual
A input pipeline registers, pattern detection, Logic Unit functionality, single
14
Send Feedback
48
A:B
30
18
18
MULT
M
25 X 18
30
25
48
C
17-Bit Shift
1
17-Bit Shift
7
Figure 2-1: 7 Series FPGA DSP48E1 Slice
www.xilinx.com
MULTSIGNOUT*
ALUMODE
4
X
0
0
Y
1
0
Z
3
MULTSIGNIN*
CARRYCASCIN*
CARRYCASCOUT*
PCOUT*
P
48
4
P
CARRYOUT
48
P
P
PATTERNDETECT
P
PATTERNBDETECT
CREG/C Bypass/Mask
48
PCIN*
UG369_c1_01_052109
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018