Dsp48E1 Tile And Interconnect - Xilinx 7 Series User Manual

DSP48E1 Tile and Interconnect

Two DSP48E1 slices and dedicated interconnect form a DSP48E1 tile (see
DSP48E1 tiles stack vertically in a DSP48E1 column. The height of a DSP48E1 tile is the
same as five configurable logic blocks (CLBs) and also matches the height of one block
RAM. The block RAM in 7 series devices can be split into two 18K block RAMs. Each
DSP48E1 slice aligns horizontally with an 18K block RAM. The 7 series devices have up to
20 DSP48E1 columns.
X-Ref Target - Figure 2-3
The 7 series devices offer from 10 to 3,600 DSP slices per device, yielding an impressive
processing power in the range of tens of GMAC/s up to thousands of GMAC/s (peak),
enabling very intensive DSP applications.
for each device in the 7 series. Refer to the product tables on
the Spartan-7, Artix-7, Kintex-7, and Virtex-7 families.
Table 2-1: Number of DSP48E1 Slices in 7 Series Devices
Total DSP48E1 Slices per
Device
7S6
7S15
7S25
7S50
7S75
7S100
7A12T
7A15T
7A25T
7A35T
7A50T
7A75T
7A100T
7A200T
7K70T
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
Architectural Highlights of the 7 Series FPGA DSP48E1 Slice
Figure 2-3: DSP48E1 Interconnect and Relative Dedicated Element Sizes
Number of DSP48E1 Columns
Device
10
20
80
120
140
160
40
45
80
90
120
180
240
740
240
www.xilinx.com
DSP48E1
Slice
DSP48E1
Slice
UG479_c1_03_060910
Table 2-1 shows the number of DSP48E1 slices
xilinx.com
Number of DSP48E1 Slices
per Device
1
1
2
2
2
2
2
2
2
2
2
3
3
9
3
Figure 2-3). The
for information on
per Column
(2)
20
20
40
60
(2)
80
80
(2)
40
(2)
60
40
(2)
60
60
(2)
80
80
(1)
100
80
19
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