Xilinx 7 Series User Manual page 51

X-Ref Target - Figure 3-5
It is important to balance the delay of the input sample and the coefficients in the cascaded
adder to achieve the correct results. The coefficients are staggered in time (wave
coefficients).
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
Slice 8
h7(n-7)
×
18
18
Slice 7
h6(n-6)
×
18
18
Slice 6
h5(n-5)
×
18
18
Slice 5
h4(n-4)
×
18
18
Slice 4
h3(n-3)
×
18
18
Slice 3
h2(n-2)
×
18
18
Slice 2
h1(n-1)
×
18
18
Slice 1
h0(n)
×
18
X(n)
18
Sign Extended from 36 Bits to 48 Bits
Figure 3-5: Adder Cascade
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Adder Tree Versus Adder Cascade
+
48 48
No Wire Shift
48
+
48
No Wire Shift
48
+
48
No Wire Shift
48
+
48
The post adders are
No Wire Shift
contained entirely in
48
dedicated silicon for
highest performance
+
and lowest power.
48
No Wire Shift
48
+
48
No Wire Shift
48
+
48
No Wire Shift
48
+
48
Zero
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Y(n–10)
UG479_c2_05_072210
51