Xilinx 7 Series User Manual page 49

In traditional FPGAs, the fabric adders are usually the performance bottleneck. The
number of adders needed and the associated routing depends on the size of the filter. The
depth of the adder tree scales as the log
tree structure shown in
The 7 series FPGA CLB allows the use of both the 6LUT and the carry chain in the same
slice to build an efficient ternary adder. The 6LUT in the CLB functions as a dual 5LUT. The
5LUT is used as a 3:2 compressor to add three input values to produce two output values.
The 3:2 compressor is shown in
X-Ref Target - Figure 3-2
B4 IN4
X(1)
B3 IN3
Y(1)
B2 IN2
Z(1)
B5 IN5
BBUS(0)
B1 IN1
SUB/
ADDB
BX
BBUS(0)
A4 IN4
X(0)
A3 IN3
Y(0)
A2 IN2
Z(0)
A5 IN5
SUB/
ADDB
AX
SUB/
ADDB
The dual 5LUT configured as a 3:2 compressor in combination with the 2-input carry
cascade adder adds three N-bit numbers to produce one N+2 bit output, as shown in the
Figure
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
Figure 3-1
ABUS(1)
0
1
VDD
IN6
ABUS(0)
0
1
VDD
IN6
Figure 3-2: Ternary Add/Sub with 3:2 Compressor
3-3, by vertically stacking the required number of slices.
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Adder Tree Versus Adder Cascade
of the number of taps in the filter. Using the adder
2
could also increase the cost, logic resources, and power.
Figure 3-2.
CY(1)
O6B
0 1
O5B
CY(0)
O6A
0 1
O5A
BMUX BBUS(1)
BQ SUM(1)
D Q
CK
AMUX BBUS(0)
AQ SUM(0)
D Q
CK
GND
UG479_c2_02_072210
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