Xilinx 7 Series User Manual page 23

Table 2-2: DSP48E1 Port Descriptions (Cont'd)
Name Direction
CECTRL
CED
CEINMODE
CEM
CEP
CLK
(1)
D
INMODE
(2)
MULTSIGNIN
(2)
MULTSIGNOUT
OPMODE
OVERFLOW
P
PATTERNBDETECT
PATTERNDETECT
(2)
PCIN
(2)
PCOUT
RSTA
RSTALLCARRYIN
RSTALUMODE
RSTB
RSTC
RSTCTRL
RSTD
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
Bit Width
In 1 Clock enable for the OPMODE and CARRYINSEL (control inputs)
registers.
In 1 Clock enable for the D (input) register.
In 1 Clock enable for the INMODE control input registers.
In 1 Clock enable for the post-multiply M (pipeline) register and the
internal multiply round CARRYIN register.
In 1 Clock enable for the P (output) register.
In 1 CLK is the DSP48E1 input clock, common to all internal registers and
flip-flops.
In 25 25-bit data input to the pre-adder or alternative input to the
multiplier. The pre-adder implements D + A as determined by the
INMODE3 signal.
In 5 These five control bits select the functionality of the pre-adder, the A,
B, and D inputs, and the input registers. These bits should default to
5'b00000 if left unconnected. These are optionally invertible,
providing routing flexibility.
In 1 Sign of the multiplied result from the previous DSP48E1 slice for
MACC extension.
Out 1 Sign of the multiplied result cascaded to the next DSP48E1 slice for
MACC extension.
In 7 Controls the input to the X, Y, and Z multiplexers in the DSP48E1 slice
(see Table
Out 1 Overflow indicator when used with the appropriate setting of the
pattern detector.
Out 48 Data output from second stage adder/subtracter or logic function.
Out 1 Match indicator between P[47:0] and the pattern bar.
Out 1 Match indicator between P[47:0] and the pattern.
In 48 Cascaded data input from PCOUT of previous DSP48E1 slice to
adder.
Out 48 Cascaded data output to PCIN of next DSP48E1 slice.
In 1 Reset for both A (input) registers.
In 1 Reset for the Carry (internal path) and the CARRYIN register.
In 1 Reset for ALUMODE (control inputs) registers.
In 1 Reset for both B (input) registers.
In 1 Reset for the C (input) register.
In 1 Reset for OPMODE and CARRYINSEL (control inputs) registers.
In 1 Reset for the D (input) register and for the pre-adder (output) AD
pipeline register.
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Description
2-7, Table 2-8, and Table 2-9).
DSP48E1 Slice Primitive
23
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