Xilinx 7 Series User Manual page 39

CARRYCASCOUT signal is also fed back into the same DSP48E1 slice via the
CARRYINSEL multiplexer.
The CARRYOUT[3] signal should be ignored when the multiplier or a ternary
add/subtract operation is used. Because a MACC operation includes a three-input adder
in the accumulator stage, the combination of MULTSIGNOUT and CARRYCASCOUT
signals is required to perform a 96-bit MACC, spanning two DSP48E1 slices. The second
DSP48E1 slice OPMODE must be MACC_EXTEND (1001000) to use both
CARRYCASCOUT and MULTSIGNOUT, thereby eliminating the ternary adder carry
restriction for the upper DSP48E1 slice. The actual hardware implementation of
CARRYOUT/CARRYCASCOUT and the differences between them are described in
Appendix A, CARRYOUT, CARRYCASCOUT, and
MULTSIGNOUT Port Logic
MULTSIGNOUT is a software abstraction of the hardware signal. It is modeled as the MSB
of the multiplier output and used only in MACC extension applications to build a 96-bit
MACC. The actual hardware implementation of MULTSIGNOUT is described in
Appendix A, CARRYOUT, CARRYCASCOUT, and
The MSB of a multiplier output is cascaded to the next DSP48E1 slice using the
MULTSIGNIN port and can be used only in MACC extension applications to build a 96-bit
accumulator. The actual hardware implementation of MULTSIGNOUT is described in
Appendix A, CARRYOUT, CARRYCASCOUT, and
PATTERNDETECT and PATTERNBDETECT Port Logic
A pattern detector has been added on the output of the DSP48E1 slice to detect if the P bus
matches a specified pattern or if it exactly matches the complement of the pattern. The
PATTERNDETECT (PD) output goes High if the output of the adder matches a set pattern.
The PATTERNBDETECT (PBD) output goes High if the output of the adder matches the
complement of the set pattern.
A mask field can also be used to hide certain bit locations in the pattern detector.
PATTERNDETECT computes ((P == pattern)||mask) on a bitwise basis and then ANDs
the results to a single output bit. Similarly, PATTERNBDETECT can detect if
((P == ~pattern)||mask). The pattern and the mask fields can each come from a distinct
48-bit configuration field or from the (registered) C input. When the C input is used as the
PATTERN, the OPMODE should be set to select a 0 at the input of the Z multiplexer. If all
the registers are reset, PATTERNDETECT is High for one clock cycle immediately after the
RESET is deasserted.
The pattern detector allows the DSP48E1 slice to support convergent rounding and
counter auto reset when a count value has been reached as well as support overflow,
underflow, and saturation in accumulators.
Overflow and Underflow Port Logic
The dedicated OVERFLOW and UNDERFLOW outputs of the DSP48E1 slice use the
pattern detector to determine if the operation in the DSP48E1 slice has overflowed beyond
the P[N] bit where N is between 1 and 46. The P register must be enabled while using
overflow and underflow ports. This is further described in the
section.
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
Simplified DSP48E1 Slice Operation
www.xilinx.com
MULTSIGNOUT.
MULTSIGNOUT.
MULTSIGNOUT.
Embedded Functions
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