Xilinx 7 Series User Manual page 30

Chapter 2: DSP48E1 Description and Specifics
The 25-bit A (A[24:0]) and 18-bit B ports supply input data to the 25-bit by 18-bit, two's
complement multiplier. With independent C port, each DSP48E1 slice is capable of
Multiply-Add, Multiply-Subtract, and Multiply-Round operations.
Concatenated A and B ports (A:B) bypass the multiplier and feed the X multiplexer input.
The 30-bit A input port forms the upper 30 bits of A:B concatenated datapath, and the
18-bit B input port forms the lower 18 bits of the A:B datapath. The A:B datapath, together
with the C input port, enables each DSP48E1 slice to implement a full 48-bit
adder/subtracter provided the multiplier is not used, which is achieved by setting
USE_MULT to NONE (or DYNAMIC).
Each DSP48E1 slice also has two cascaded input datapaths (ACIN and BCIN), providing a
cascaded input stream between adjacent DSP48E1 slices. The cascaded path is 30 bits wide
for the A input and 18 bits wide for the B input. Applications benefiting from this feature
include FIR filters, complex multiplication, multi-precision multiplication and complex
MACCs.
The A and B input port and the ACIN and BCIN cascade port can have 0, 1, or 2 pipeline
stages in its datapath. The dual A, D, and pre-adder port logic is shown in
dual B register port logic is shown in
attributes. Attributes AREG and BREG are used to select the number of pipeline stages for
A and B direct inputs. Attributes ACASCREG and BCASCREG select the number of
pipeline stages in the ACOUT and BCOUT cascade datapaths. The allowed attribute
settings are shown in
through paths, optional registers, or cascaded inputs. The data port registers allow users to
typically trade off increased clock frequency (i.e., higher performance) versus data latency.
X-Ref Target - Figure 2-7
A
ACIN
D
30
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Figure
Table 2-3. Multiplexers controlled by configuration bits select flow
A2
30
A1
CEA1 RSTA
CEA2 RSTA
INMODE[0]
D
25 INMODE[2]
CED RSTD
Figure 2-7: Dual A, D, and Pre-adder Logic
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2-8. The different pipestages are set using
30
30
0
INMODE[1]
1
+
AD
–
25
INMODE[3]
CEAD RSTD
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
Figure 2-7. The
ACOUT
X MUX
25
A MULT
25
UG369_c1_07_040914