Xilinx 7 Series User Manual page 25

accumulators. In conjunction with the logic unit, the pattern detector can be extended to
perform a 48-bit dynamic comparison of two 48-bit fields. This enables functions such as
A:B NAND C = = 0, or A:B (bitwise logic) C = = Pattern to be implemented.
Figure 2-5
control the selects of X, Y, and Z multiplexers, feeding the inputs to the adder/subtracter or
logic unit. In all cases, the 43-bit partial product data from the multiplier to the X and Y
multiplexers is sign extended, forming 48-bit input datapaths to the adder/subtracter.
Based on 43-bit operands and a 48-bit accumulator output, the number of guard bits (i.e.,
bits available to guard against overflow) is 5. To extend the number of MACC operations,
the MACC_EXTEND feature should be used, which allows the MACC to extend to 96 bits
with two DSP48E1 slices. If A port is limited to 18 bits (sign-extended to 25), then there are
12 guard bits for the MACC. The CARRYOUT bits are invalid during multiply operations.
Combinations of OPMODE, ALUMODE, CARRYINSEL, and CARRYIN control the
function of the adder/subtracter or logic unit.
X-Ref Target - Figure 2-5
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
shows the DSP48E1 slice in a very simplified form. The seven OPMODE bits
P
A:B
D
+
A
X
B
All 1s
C
All 0s
PCIN
Shifters
Figure 2-5: Simplified DSP Slice Operation
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Simplified DSP48E1 Slice Operation
OPMODE Controls Behavior
X
Y
Z
OPMODE, CARRYINSEL,
and ALUMODE Control
Behavior
P
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