Xilinx 7 Series User Manual page 41

Two's Complement Multiplier
The two's complement multiplier in the DSP48E1 slice in
complement input and an 18-bit two's complement input. The multiplier produces two
43-bit partial products. The two partial products together give an 86-bit result at the output
of the multiplier, as shown in
products is supported with a 17-bit, right-shifted, cascaded output bus. The right shift is
used to right justify the partial products by the correct number of bits. This cascade path
feeds into the Z multiplexer, which is connected to the adder/subtracter of an adjacent
DSP48E1 slice. The multiplier can emulate unsigned math by setting the MSB of an input
operand to zero.
Figure 2-15
Using the register provides increased performance with an increase of one clock latency.
X-Ref Target - Figure 2-15
Adder/Subtracter or Logic Unit
The adder/subtracter or logic unit output is a function of control and data inputs (see
Figure
CARRYINSEL signals. The ALUMODE signals choose the function implemented in the
adder/subtracter. Thus, the OPMODE, ALUMODE, and CARRYINSEL signals together
determine the functionality of the embedded adder/subtracter/logic unit. When using the
logic unit, the multiplier must not be used. The values of OPMODEREG and
CARRYINSELREG must be identical.
As with the input multiplexers, the OPMODE bits specify a portion of this function. The
symbol ± in the table means either add or subtract and is specified by the state of the
ALUMODE control signal. The symbol ":" in the table means concatenation. The outputs
of the X and Y multiplexer and CIN are always added together. Refer to
Inputs, page
Two-Input Logic Unit
In 7 series devices, the capability to perform an addition, subtraction, and simple logic
functions in the DSP48E1 slice exists through use of a second-stage, three-input adder.
Table 2-13
input adder/subtracter/logic unit. The table also lists the settings of the control signals,
namely OPMODE and ALUMODE.
Setting OPMODE[3:2] to "00" selects the default "0" value at the Y multiplexer output.
OPMODE[3:2] set to "10" selects "all 1s" at the Y multiplexer output. OPMODE[1:0]
selects the output of the X multiplexer, and OPMODE[6:4] selects the output of the
Z multiplexer.
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
Figure
shows an optional pipeline register (MREG) for the output of the multiplier.
86
A or AD
X
B
Figure 2-15: Two's Complement Multiplier Followed by Optional MREG
2-16). The data inputs to the adder/subtracter are selected by the OPMODE and the
35.
lists the logic functions that can be implemented in the second stage of the three
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Simplified DSP48E1 Slice Operation
Figure 2-14
2-15. Cascading of multipliers to achieve larger
43
43
Optional
MREG
accepts a 25-bit two's
Partial Product 1
Partial Product 2
UG369_c1_15_051209
ALUMODE
41
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