Xilinx 7 Series User Manual page 46

Chapter 2: DSP48E1 Description and Specifics
X-Ref Target - Figure 2-20
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Overflow is caused by addition when the value at the output of the
adder/subtracter/logic unit goes over 3. Adding 1 to the final value of 0..0011 gives
0..0100 as the result, which causes the PD output to go to 0. When the PD output goes
from 1 to 0, an overflow is flagged.
Underflow is caused by subtraction when the value goes below –4. Subtracting 1 from
1..1100 yields 1..1010 (–5), which causes the PBD output to go to 0. When the PBD
output goes from 1 to 0, an underflow is flagged.
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x x x
PBD Caused by Underflow
Underflow
Figure 2-20: Underflow Condition in the Pattern Detector
PD is 1 if P == pattern or mask
PBD is a 1 if P == patternb or mask
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0 .. 0000
x 1 .. 1111 1 .. 1110 1 .. 1101 1 .. 1100 1 .. 1010
High to Low
UG369_c1_20_051209
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018