Phase Descriptions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Test Number:
Function:
3
This test verifies that DMA1 from the SBD DPDRAM to the PORTS RAM is
functional.
Procedure:
Data is written (PIa) to the SBD DPDRAM. That data is transferred to the
PORTS RAM, and then it is compared for integrity.
Hardware Tested:
The PORTS DMA1 (INTEL 80186) from the SBD to the PORTS card is tested.
Data Returned:
The test number that failed, the actual data, and the expected data are returned.
Test Number:
Function:
Procedure:
4
This test verifies that DMA1 from the PORTS RAM to the SBD DPDRAM is
functional.
Data is written to the PORTS RAM. That data is transferred to the SBD
DPDRAM, and it is compared for integrity.
Hardware Tested:
The PORTS DMA1 (INTEL 80186) from the PORTS to the SBD is tested.
Data Returned:
The test number that failed, the actual data, and the expected data are returned.
8-28 OFF-LINE DIAGNOSTIC MANUAL