Phase #6 - Cpu Chip Select Test; Phase #6 Tests - AT&T 3B2 Off-Line Diagnostic Manual

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Phase #6 - CPU Chip Select Test
Phase Name:
Type:
Function:
Tests:
Time:
Warnings:
Notes:
Phase #6 Tests
Upper Chip Select Register Tests (cpu_I)
Demand
This phase tests the operation of the Upper Memory Chip Select (UMCS),
Peripheral Access Chip Select (P ACS), Middle Memory Chip Select (MMCS),
and Middle Peripheral Chip Select (MPCS) registers of the INTEL 80186 CPU.
Tests 1 through 12 - check the UMCS register.
Tests 13 through 29 - check the PACS register.
Tests 30 through 37 - check the MMCS register.
Tests 38 through 48 - check the MPCS register.
2 seconds
None
If any test in this phase fails, the following hardware may be faulty:
• INTEL 80186 Microprocessor
• INTEL 80186 Microprocessor interface to the CTC Address/Data bus.
Test Numbers: 1 through 12
Function: These tests verify that the UMCS register is functional.
Procedure: A valid data pattern is written to the register and verified with a read.
Hardware Tested: The UMCS register is tested.
Data Returned: The test number that failed, the actual data, and the expected data are returned.
Notes: None
Test Numbers: 13 through 29
Function: These tests verify that the PACS register is functional.
Procedure: A valid data pattern is written to the register and verified with a read.
Hardware Tested: The P ACS register is tested.
Data Returned: The test number that failed, the actual data, and the expected data are returned.
Notes: None
CARTRIDGE TAPE CONTROLLER DIAGNOSTICS 5-9