Phase #4 - Math Accelerator Unit #1; Phase #4 Tests - AT&T 3B2 Off-Line Diagnostic Manual

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Phase #4 - Math Accelerator Unit #1
Phase Name:
Type:
Function:
Tests:
Time:
Warnings:
Notes:
Phase #4 Tests
WE 32106 Math Accelerator Unit (MAU) (mau1_tst)
Normal
This phase tests for the presence of a MAU device. If it is found, the phase
pattern tests the MAU Data bus, operand registers FO through F3, and the
MAU Data register.
Test 1 - determines if a MAU is present on the SBD under test.
Test 2 - pattern checks the MAU Data bus by walking a one through a field
of zeros as a single precision operand to register FO.
Tests 3 through 6 - pattern checks the MAU registers FO through F3 as a
double-extended precision operand with a modified data pattern of Ox55's and
Oxaa's.
Test 7 - pattern checks the MAU Data register as a double-extended precision
operand with a modified data pattern of Ox55's and Oxaa's.
1 second
None
If a MAU is not detected on the board under test, this test phase displays NTR
(No Test Run) and returns an NTR condition. All operand pattern tests are
checked for register-to-register cross talk.
Test Number: 1
Function: This test determines if the MAU is present on the SBD.
Procedure: A SPOP NOP is issued to see if the MAU device is present.
Hardware Tested: The MAU is tested.
Data Returned: A warning message indicating diagnostics not run is returned.
Notes: None
Test Number: 2
Function: This test pattern checks the MAU Data bus.
Procedure: A one is walked through a field of zeros as a single precision operand by
moving the operand to and from register FO.
Hardware Tested: The MAU is tested.
Data Returned: The number of the test that failed, the actual data, and the expected data are
returned.
Notes: None
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