AT&T 3B2 Off-Line Diagnostic Manual page 255

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Phase Descriptions
Test Numbers:
Function:
Procedure:
5 and 6
These tests verify that the lower RAM and refresh circuitry are functioning
properly.
All memory locations are read, expecting A's, and then all memory is written
with the following patterns in ascending order:
pat(00)=OxF606 pat(08)=OxF603 pat(16)=Ox7FB8 pat(24)=Ox401B
pat(01)=OxE727 pat(09)=OxD732 pat(17)=Ox6E99 pat(25)=Ox612A
pat(02)=OxD25A pat(10)=OxA245 pat(18)=Ox59F4 pat(26)=OxOA5F
pat(03)=OxC37B pat(11)=Ox8374 pat(19)=Ox48D5 pat(27)=Ox2B6E
pat(04)=OxBAEC pat(12)=Ox1988 pat(20)=Ox3D41 pat(28)=OxBD96
pat(05)=OxABCD pat(13)=Ox38B9 pat(21)=Ox2C60 pat(29)=Ox9CA7
pat(06)=Ox91A2 pat(14)=Ox5FCO pat(22)=Ox141F pat(30)=OxE5DC
pat(07)=Ox8083 pat(15)=Ox7EF1 pat(23)=Ox053E pat(31)=OxC4ED
The patterns are written according to the following formula:
memory location(i) = pat(i modulo 32)
where i = {O, 1, 2 ... 32K} where K=1024
a memory location = 16 bits.
All memory locations will be read in ascending order after a 1-second delay to
test the refresh circuitry. The refresh rate is each 2.048 milliseconds. The time
needed to read or write all 64 kilobytes of memory (16 bits on each read or
write) is approximately 20.0 milliseconds (125 nanoseconds per cycle, it takes 5
cycles to perform a read or write). A delay of 1 second, in addition to the 20.0
milliseconds needed to write all memory, is sufficient to test the refresh
circuitry. This phase executes from the lower 64 kilobytes of RAM.
Hardware Tested: The lower RAM and refresh circuitry are tested.
Data Returned: The test number that failed, the expected data, and the actual data are returned.
Notes: None
CARTRIDGE TAPE CONTROLLER DIAGNOSTICS 5-7