- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Phase Descriptions
Test Numbers:
18 through 34
Function:
These tests verify that the TimerO Maximum Count A (MCA) register is
functional.
Procedure:
A valid data pattern is written to the register and verified with a read.
Hardware Tested:
The TimerO MCA register is tested.
Data Returned:
The test number that failed, the actual data, and the expected data are returned.
Test Numbers:
35 through 51
Function:
These tests verify that the TimerO Maximum Count B (MCB) register is
functional.
Procedure:
A valid data pattern is written to the register and verified with a read.
Hardware Tested:
The TimerO MCB register is tested.
Data Returned:
The test number that failed, the actual data, and the expected data are returned.
Test Numbers:
52 through 59
Function:
These tests verify that the TimerO Mode register is functional.
Procedure:
A valid data pattern is written to the register and verified with a read.
Hardware Tested:
The TimerO Mode register is tested.
Data Returned:
The test number that failed, the actual data, and the expected data are returned.
Test Numbers:
60 through 77
Function:
These tests verify that the Timerl Count register is functional.
Procedure:
A valid data pattern is written to the register and verified with a read.
Hardware Tested:
The Timerl Count register is tested.
Data Returned:
The test number that failed, the actual data, and the expected data are returned.
Test Numbers:
78 through 94
Function:
These tests verify that the Timerl MCA register is functional.
Procedure:
A valid data pattern is written to the register and verified with a read.
Hardware Tested:
The Timerl MCA register is tested.
Data Returned:
The test number that failed, the actual data, and the expected data are returned.
NETWORK INTERFACE DIAGNOSTICS
7-13
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