AT&T 3B2 Off-Line Diagnostic Manual page 545

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Phase Descriptions
Phase #2 Tests
Test Number: 1
Function: This test checks that a faulty MAU can be detected.
Procedure: A divide-by-zero is performed, and the fact that an exception was generated is
confirmed. Then, the divide-by-zero fault is inhibited, and the process is
repeated. The fact that an exception is not generated is confirmed. In both
cases, the MAU-ASR is checked to ensure that the correct flags were set.
Hardware Tested: The MAU is tested.
Data Returned: The failing test number (last number displayed on the system console prior to
failure) is returned.
Notes: None
Test Number: 2
Function: This test checks the ASR Invalid Operation "Sticky" (IS) and Mask bits (1M).
Procedure: An Integer to Float Conversion (ITOF) is performed with the source specified as
MAU register FO. It is confirmed that an exception was generated. Then,
Invalid Operation exceptions are inhibited, and the procedure is repeated. It is
confirmed that an exception was not generated. In both cases, it is checked
that the correct MAU-ASR flags were set.
Hardware Tested: The MAU is tested.
Data Returned: The failing test number (last number displayed on the system console prior to
failure) is returned.
Notes: None
Test Number: 3
Function: This test checks the ASR Overflow "Sticky" (OS) and Mask bits (OM).
Procedure: An Overflow exception is forced by using the MAU division instruction. It is
confirmed that an exception was taken. Then, Overflow exceptions are
inhibited, and the procedure is repeated. It is confirmed that an exception was
not taken. In both scenarios, the MAU-ASR is checked for correct flag
generation.
Hardware Tested: The MAU is tested.
Data Returned: The failing test number (last number displayed on the system console prior to
failure) is returned.
Notes: None
MATH ACCELERATOR UNIT 12-5