AT&T 3B2 Off-Line Diagnostic Manual page 422

Phase Descriptions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Phase #19 - PORTS-DUART 0 External Loop
Phase Name:
Type:
Function:
Tests:
Time:
Warnings:
Notes:
PORTS - DUART (SC2681) 0 External Loop (duartO_2)
Interactive
This phase verifies the ability of Dual Universal Asynchronous
Receiver/Transmitter (DUART) 0 to do external loop around at various baud
rates.
Test 1 - checks the Port 1 DTR.
Tests 2 through 11 - check the external loop of the ASCII characters through
DUART 0, Port 1.
Test 12 - checks the Port 2 DTR.
Tests 13 through 22 - check the external loop of the ASCII characters through
DUART 0, Port 2.
Test (23) - checks the ability of the DUART to send an interrupt when the
Receive Data register on DUART 0, Port 1 is enabled and has received a
character.
Test (24) - checks the ability of the DUART to send an interrupt when the
Transmit Data register on DUART 0, Port 1 is enabled and after a character has
been transmitted.
Test (25) - checks the ability of the DUART to send an interrupt when the
Receive Data register on DUART 0, Port 2 is enabled and has received a
character.
Test (26) - checks the ability of the DUART to send an interrupt when the
Transmit Data register on DUART 0, Port 2 is enabled and after a character has
been transmitted.
Test (27) - checks the ability of the DUART to send an interrupt when
Receive buffer full (3 characters) is detected on DUART 0, Port 1.
Test (28) - checks the ability of the DUART to send an interrupt when
Receive buffer full (3 characters) is detected on DUART 0, Port 2.
Test (29) - checks the ability of the DUART to send an interrupt when a
break character is detected on DUART 0, Port 1.
Test (30) - checks the ability of the DUART to send an interrupt when a
break character is detected on DUART 0, Port 2.
Test (31) - checks the ability of the DUART to send an interrupt when
"Counter Ready" is detected on DUART O.
7 seconds
This phase requires two special loop around plugs. They must be connected to
the first and second serial jack connections of the PORTS card under test.
Figure 8-1 shows the loop around plug wiring. The DTR is implemented by
using bits 0 and 1 of the DUART general purpose Output register. These two
outputs are inverted and internally strapped to bits 0 and 1 of the general
purpose Input register.
8-44 OFF-LINE DIAGNOSTIC MANUAL