AT&T 3B2 Off-Line Diagnostic Manual page 170

Version 3 Hardware System Board Diagnostics - - - - - - - - - - - - - - - - - - - - -
Test Number:
Function:
Procedure:
19
This test verifies that Fault Latch registers contain the corresponding data after
a DMA operation on a faulted address.
The test procedure is as follows:
1.
Initialize B-side DUART to local loop around mode.
2. Initialize DMAC for DMA operation through the DUART.
3. Next enable the force Error Correction Coding (ECC) syndrome.
4. Write data to faulted memory address and disable FECC syndrome.
5. Request DMA job and delay for job completion.
6. Verify that Fault Latch register 1 contains the faulted address and that
Fault Latch register 2 contains status that Input/Output (I/O) was
master at time of fault.
7. Verify Control Status and Error Register (CSER) indicates that Fault
registers were loaded.
8. Restore faulted address.
Hardware Tested: The 9517 DMAC and Fault Latch registers 1 and 2 are tested.
Data Returned: The failing test number (last number displayed on the system console before
failure), as well as error data presented are returned.
Notes: None
Test Number:
Function:
Procedure:
20
This test confirms that the DMAC can perform a DMA operation at every
megabyte of memory.
The test procedure is as follows:
1.
Initialize B-side DUART to local loop around mode.
2. Initialize DMAC for DMA operation through the DUART. Job is to
transmit 4 bytes.
3. Request DMA job and delay for job completion.
4. Check B side of DUART for FIFO Full bit set in DUART Status register
and confirm reception of 4 bytes.
Hardware Tested: The 9517 DMAC is tested.
Data Returned: The failing test number (last number displayed on the system console before
failure), as well as error data presented are returned.
Notes: None
3-130 OFF-LINE DIAGNOSTIC MANUAL