Phase #18 Tests - AT&T 3B2 Off-Line Diagnostic Manual

Version 3 Hardware System Board Diagnostics - - - - - - - - - - - - - - - - - - - - -
Phase #18
Phase Name:
Type:
Function:
Tests:
Time:
Warnings:
Notes:
Phase #18 Tests
Test Numbers:
Function:
Procedure:
Direct Memory Access Controller Diagnostics
Direct Memory Access Controller (DMAC) (dmac_tst)
Normal
This phase tests the registers and operations of the AMD 9517 Direct Memory
Access Controller (DMAC).
Tests 1 through 16 - perform pattern tests on the Current Address register
and the Current Word register for all channels.
Test 17 - checks DMA operation using DUART B in local loop around mode.
Test 18 - checks DMA operation using DUART A in local loop around mode.
Test 19 - checks Fault Latch registers one and two for correct failing address
data after an I/O fault has occurred.
Test 20 - checks DMA operation using DUART B in local loop around mode
and perform DMA operations at every megabyte of memory.
2 seconds
None
None
1 through 16
These tests perform a pattern test on each of the Current Address and Current
Word registers for each channel.
The test procedure is as follows:
1. Clear byte pointer in DMAC.
2. Load pattern into lower Channel register under test.
3. Clear byte pointer in DMAC.
4. Read and confirm lower data pattern reception for Channel register
under test.
5. Read and confirm upper data pattern reception for Channel register
under test.
Hardware Tested: The 9517 DMAC is tested.
Data Returned: The failing test number (last number displayed on the system console before
failure) and the expected versus the read pattern are returned.
3-128 OFF-LINE DIAGNOSTIC MANUAL