AT&T 3B2 Off-Line Diagnostic Manual page 319

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Phase Descriptions
Phase #15 Test
Test Number:
Function:
Procedure:
1
This test verifies data transmission through Channel A of the ISC USART.
A block of data (Ox700 bytes) is generated which contains the following data
patterns:
OxOO
Oxff
Oxaa
Ox55
incrementing pattern
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
walking ones 256 bytes
alternating bytes
of OxOO and Oxff
256 bytes
Hardware Tested: This test checks the ISC USART. Other major components which have already
been verified to a degree are also tested.
If this phase fails, the following hardware may be faulty:
• ISC Channel A USART
• ISC external Direct Memory Access Controller (DMAC) chip
• INTEL 80186 CPU interface to the ISC Address/Data bus
• Missing or faulty loopback cable.
Data Returned: The test number that failed, the actual data, and the expected data are returned.
Additional error conditions returned are as follows:
• Lost DCD or missing loop plug
• Lost CTS
• Overrun error
• CRC error
• Bad Direct Memory Access (DMA) receive terminal count
• Bad DMA transmit terminal count
• ISC receiving incomplete or missing loop plug
• Data miscompare in ISC
• Data miscompare in 3B2 computer.
INTELLIGENT SERIAL CONTROLLER DIAGNOSTICS 6-27