AT&T 3B2 Off-Line Diagnostic Manual page 291

Chapter 6: Intelligent Serial Controller Diagnostics
Introduction
Phase Descriptions
Phase #1 - Common I/O and Peripheral Sanity
Phase #1 Test
Phase #2 - PCSR Read/Write Test
Phase #2 Tests
Phase #3 - Upper RAM Verification Test
Phase #3 Tests
Phase #4 - Lower RAM Verification Test
Phase #4 Tests
Phase #5 - Unique Address Test
Phase #5 Test
Phase #6 - ROM Check Sum
Phase #6 Test
Phase #7 - Upper Chip Select Register Test
Phase #7 Tests
Phase #8 - DMA Control Registers Test
Phase #8 Tests
Phase #9 - CPU Writable Register Test
Phase #9 Tests
Phase #10 - Interrupt Control Register Test
Phase #10 Tests
Phase #11 - Download/Upload Common I/O Test
Phase #11 Test
Phase #12 - Verify DOS/ZOMBIE Commands Test
Phase #12 Tests
Phase #13 - External DMA Tests
Phase #14 - Enter ISC Debug Mode Test
Phase #14 Test
Phase #15 - ISC Channel A Loopback Test
Phase #15 Test
Phase #16 - ISC Channel B Loopback Test
Phase #16 Test
Phase #17 - ISC Channel A-to-B Loopback Test
Phase #17 Test
Phase #18 - ISC Channel B-to-A Loopback Test
Phase #18 Test
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