AT&T 3B2 Off-Line Diagnostic Manual page 227

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Phase Descriptions
Phase #13 Tests
Test Number: 1
Function: This test ensures that a Level 15 interrupt is generated when the MPB Control
and Status Register (CSR) INTIS bit is set.
Procedure: Drop the CPUs interrupt Level to 14 so as to block all normal interrupts below
Level 15, set the MPB CSR INTIS bit and confirm that an interrupt is
generated and that the Control Status and Error Register (CSER) accurately
reflects the correct scenario.
Hardware Tested: The MPB CSR, the Interrupt System, and the System CSER are tested.
Data Returned: Interrupt handler data from the CSER read is returned.
Notes: None
Test Number: 2
Function: This test ensures that a Level 15 interrupt is generated when the MPB CSR
INTIS bit is set by the MPB.
Procedure: Drop the CPUs interrupt Level to 14 so as to block all normal interrupts below
Level 15, request the MPB to run .. /bpb/bintl_tstO and confirm that an
interrupt is generated and that the CSER accurately reflects the correct scenario.
Hardware Tested: The MPB, the MPB CSR, the Interrupt System, and the System CSER are
tested.
Data Returned: Interrupt handler data from the CSER read is returned.
Notes: None
Test Number: 3
Function: This test ensures that the MPB CSR bit, Interrupt Central Processing Unit
(INTCPU), generates a local Level 15 interrupt to the MPB Processor.
Procedure: Drop the MPB Processor interrupt mask to Level 14. Set the MPB CSR bit to
INTCPU. Confirm a Level 15 interrupt was taken.
Hardware Tested: The MPB Interrupt System and the MPB CSR are tested.
Data Returned: Interrupt handler data from the MPB CSR read is returned.
Notes: None
MULTIPROCESSOR DIAGNOSTICS 4-45