AT&T 3B2 Off-Line Diagnostic Manual page 242

Phase Descriptions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Test Number: 2
Function: This test checks all memory accesses on a word basis with alternate data
patterns throughout memory range.
Procedure: Various patterns are written and then read.
Hardware Tested: The MMU Data Cache [for example, Physical Cache (PCACHE)] is tested.
Data Returned: The failing address, expected value, and actual value read are returned.
Notes: None
Tests Numbers:
Function:
Procedure:
3 through 5
These tests check variable size accesses.
Test 3 - writes words and reads back as shorts. Increment address by 1000.
Test 4 - writes two shorts and reads back as bytes. Increment address by
1000.
Test 5 - writes and reads 4 bytes. Increment address by 1000.
Hardware Tested: The MMU Data Cache (for example, PCACHE) is tested.
Data Returned: The failing address, expected value, and actual value read are returned.
Notes: None
Test Number: 6
Function: This test checks the tag field of the PCACHE.
Procedure: Access every entry in the cache, change a Tag bit, and repeat.
Hardware Tested: The MMU Data Cache (for example, PCACHE) is tested.
Data Returned: The failing address, expected value, and actual value read are returned.
Notes: None
4-60 OFF-LINE DIAGNOSTIC MANUAL