Phase Descriptions - AT&T 3B2 Off-Line Diagnostic Manual

Chapter 5: Cartridge Tape Controller Diagnostics
Introduction
5-1
Phase Descriptions
Phase #1 - Common I/O and Peripheral Sanity Test
Phase #1 Test
Phase #2 - PCSR Write/Read Test
Phase #2 Tests
Phase #3 - Upper RAM Write/Read Test
Phase #3 Tests
Phase #4 - Lower RAM Write/Read Test
Phase #4 Tests
Phase #5 - ROM Check Sum Test
Phase #5 Test
Phase #6 - CPU Chip Select Test
Phase #6 Tests
Phase #7 - CPU DMA Internal Test
Phase
#
7 Tests
Phase #8 - CPU Timer Test
Phase #8 Tests
Phase #9 - CPU Interrupt Controller Test
Phase #9 Tests
Phase #10 - CPU Lower Chip Select Test
Phase #10 Tests
Phase #11 - Programmed Input/Output (PIO) Byte Test
Phase #11 Tests
Phase #12 - Programmed Input/Output (PIO) Word Test
Phase #12 Tests
Phase #13 - DMA Transfer Byte Test
Phase #13 Tests
Phase #14 - DMA Transfer Word Test
Phase #14 Tests
Phase #15 - CTC/DMAC Register Test
Phase #15 Tests
Phase #16 - CTC Tape/DMAC Test
Phase
#
16 Tests
Phase #17 - CTC Floppy /DMAC Test
Phase
#
17 Tests
Phase #18 - Fast CTC Tape/DMAC Test
Phase
#
18 Tests
5-2
5-2
5-2
5-3
5-3
5-4
5-4
5-6
5-6
5-8
5-8
5-9
5-9
5-11
5-11
5-14
5-14
5-18
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TABLE OF CONTENTS