Phase #21 Tests - AT&T 3B2 Off-Line Diagnostic Manual

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Phase #21 - Counter/Timer and Parallel I/O Test
Phase name:
Type:
Function:
Tests:
Time:
Warnings:
Notes:
Phase #21 Tests
Counter/Timer and Parallel I/O Test (cntr_tmr)
Demand
This phase tests the operation of the three counter/timers.
Tests 1 through 32 - walk a one through a field of zeros and a zero through a
field of ones on both Ports A and B with the Enable bit turned off.
Tests 33 and 34 - verify Counters 1 and 2 using the input clock coming in
from the TRXC of the SCC.
Tests 35 through 37 - verify that each of the three timers can generate
in terru pts.
40 seconds
None
The Counter 3 test resides in Phase 26 because it requires a clock coming in
from the external cable
Test Numbers: 1 through 32
Function: These tests verify the operation of Ports A and B.
Procedure: Walk a one through a field of zeros and a zero through a field of ones on both
Ports A and B with the Enable bit turned off.
Hardware Tested: The 8536 Counter/Timer chip is tested.
Data Returned: None
Notes: The following data is written to Ports A and B.
Test Number Port Value
1
A
OxOl
2 A Oxfe
3 B OxOl
4 B Oxfe
5 A Ox02
6 A Oxfd
7
B Ox02
8 B Oxfd
9
A Ox04
10 A Oxfb
11
B Ox04
12
B
Oxfb
13 A Ox08
14
A
Oxf7
GENERAL PURPOSE SYNCHRONOUS CONTROLLER 16-33