AT&T 3B2 Off-Line Diagnostic Manual page 240

Phase Descriptions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Phase #18 - MPB Physical Cache Diagnostics
Phase Name:
Type:
Function:
Tests:
Time:
Warnings:
Notes:
Physical Cache (bpc1_tst)
Normal
This phase tests the physical Memory Management Unit (MMU) cache memory
by performing the following tests:
Test 1 - checks that the double-bit memory fault works with the MMU cache
on.
Test 2 - checks all memory accesses on a word basis with various data
patterns throughout cache memory range; OO's followed by FF's followed by
random patterns.
Test 3 - checks memory accesses by writing words and reading back two half
words.
Test 4 - checks memory accesses by writing two half words and reading back
4 bytes.
Test 5 - checks memory accesses by writing and reading 4 bytes.
Test 6 - checks PCACHE tag fields.
10 seconds
None
These test phases will only be exercised on a PBus MPB.
Only a WE 32201, Version 2.3 or later supports caching. The MMUVR register
has the version encoded in its two low-order hexadecimal digits. If caching is
not supported by the MPB, an appropriate message is displayed and the phase
exits with status of NTR (No Tests Run).
This phase works by turning on the cache and performing accesses that are
expected to hit the cache.
4·58 OFF·LlNE DIAGNOSTIC MANUAL