Phase #5 - Extended Dynamic Random Access Memory (Dram) Diagnostics - AT&T 3B2 Off-Line Diagnostic Manual

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Phase' #5 - Extended Dynamic Random Access Memory
(DRAM) Diagnostics
Phase Name:
Type:
Function:
Tests:
Extended Oynamic Memory Test (edraIIL-tst)
Oemand
This phase tests the dynamic memory by performing the following tests:
Test 1 - checks all memory accesses on a word basis, checking for shorted
address lines.
Test 2 - checks all memory accesses on a word basis with alternate data
patterns through memory range. A pattern of 55's followed by aa's.
Test 3 - verifies dynamic memory is being refreshed by storing data pattern in
memory, delaying 1 minute and confirming data retention. Repeat test with
complement of previous data test pattern.
Test 4 - checks memory accesses by writing words and reading back two half
words.
Test 5 - checks memory accesses by writing two half words and reading back
four bytes.
Test 6 - checks memory accesses by writing and reading 4 bytes.
Tests 7 through 16 - force ECC syndrome for all single-bit errors in bits 015
through 06 by walking a one through a field of zeros using the following
binary memory half word:
015 0605 00
0000000000 001111
(05 through 00 are Check bits)
Tests 17 through 26 - force ECC syndrome for all single bit errors in bits 031
through 022 by walking a one through a field of zeros using the following
binary memory half word:
031 022 021 016 (021 through 016 are Check bits)
0000000000 001111
Tests 27 through 36 - force ECC syndrome for all single-bit errors in bits 015
through 06 by walking a zero through a field of ones using the following
binary memory half word:
015 0605 00
1111111111 000000
(05 through 00 are Check bits)
Tests 37 through 46 - force ECC syndrome for all single-bit errors in bits 031
through 022 by walking a zero through a field of ones using the following
binary memory half word:
031 022 021 016 (021 through 016 are Check bits)
1111111111 000000
SYSTEM BOARD DIAGNOSTICS 3-79