AT&T 3B2 Off-Line Diagnostic Manual page 706

Phase Descriptions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Test Number Port Value
15
B Ox08
16
B Oxf7
17 A
Oxl0
18 A Oxef
19 B Oxl0
20
B Oxef
21 A Ox20
22 A Oxdf
23 B Ox20
24 B Oxdf
25 A Ox40
26 A Oxbf
27
B Ox40
28
B Oxbf
29 A Ox80
30
A Ox7f
31
B Ox80
32
B Ox7f
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Test Numbers: 33 and 34
Function: These tests check Counters 1 and 2 using the input clock coming in from the
TRXC of the Serial Communication Controller (SCC).
Procedure: Program the Counter/Timer (CTR/TMR) to take its input clock for Timerl and
Timer2 from the TRXC pin of the SCC.
Hardware Tested: The 8536 Counter/Timer chip is tested.
Data Returned: None
Test Numbers: 35 through 37
Function: These tests verify that each of the three timers can generate interrupts.
Procedure: Program each of the three timers to use their internal clock sources and
interrupt when they have completely counted down.
Hardware Tested: The 8536 Counter/Timer chip is tested.
Data Returned: None
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