Phase #11 - Programmed Input/Output (Pio) Byte; Phase #11 Tests - AT&T 3B2 Off-Line Diagnostic Manual

Phase Descriptions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Phase #11 - Programmed Input/Output (PIO) Byte
Phase Name:
Type:
Function:
Tests:
Time:
Warnings:
Notes:
Phase #11 Tests
NI Byte PIO (pio_l)
Demand
This phase tests the NI card interface to the 3B2 computer I/O bus.
Test 1 - tests the data pattern OxOl at every address in a page of SBD
DPDRAM.
Test 2 - tests the data pattern Ox02 at every address in a page of SBD
DPDRAM.
Test 3 - tests the data pattern Ox04 at every address in a page of SBD
DPDRAM.
Test 4 - tests the data pattern Ox08 at every address in a page of SBD
DPDRAM.
Test 5 - tests the data pattern Oxl0 at every address in a page of SBD
DPDRAM.
Test 6 - tests the data pattern Ox20 at every address in a page of SBD
DPDRAM.
Test 7 - tests the data pattern Ox40 at every address in a page of SBD
DPDRAM.
Test 8 - tests the data pattern Ox80 at every address in a page of SBD
DPDRAM.
40 seconds
None
This phase performs PIO (write and read) in bytes. If any test in this phase
fails, the following hardware may be faulty:
• INTEL 80186 Microprocessor
• INTEL 80186 Microprocessor interface to the NI Address/Data bus
• Interface between the NI card and the 3B2 computer I/O bus.
Test Numbers: 1 through 8
Function: These tests verify the operation of the NI card interface to the 3B2 computer
I/O bus.
Procedure: A one is walked through a field of zeros at every address of a page of System
Board (SBD) Dual Port Dynamic Random Access Memory (DPDRAM) and
verified with a read.
Hardware Tested: The interface between the NI card and the 3B2 computer I/O bus is tested.
Data Returned: A byte value read from SBD DPDRAM, a short value read from SBD
DPDRAM, and the SBD DPDRAM failing address are returned.
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