Phase #3 Tests - AT&T 3B2 Off-Line Diagnostic Manual

Phase Descriptions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Phase #3 - Upper RAM Write/Read Test
Phase Name:
Type:
Function:
Tests:
Time:
Warnings:
Notes:
Phase #3 Tests
Test Numbers:
Function:
Procedure:
XDC Upper RAM
Demand
This phase diagnoses and reports any errors in the operation of the XDC upper
RAM and refresh circuitry.
Tests 1 through 4 - walk data patterns through the upper 64 kilobytes of
RAM.
Test 5 - checks the upper 64 kilobytes of the upper RAM and refresh
circuitry.
12 seconds
None
None
1 through 4
These tests check the operation of the upper RAM.
The following test sequence is used to test the upper RAM (addresses Ox80000
through Ox9fffe):
1. All memory locations are written with O's in ascending (small addresses
to large addresses) order.
2. All memory locations are read, expecting O's, and then all memory is
written with l's in descending order.
3. All memory locations are read, expecting l's, and then all memory is
written with 5's in ascending order.
4. All memory locations are read, expecting 5's, and then all memory is
written with A's in descending order.
Hardware Tested: The upper RAM locations are tested.
Data Returned: The number of the failing test, the actual data, and the expected data are
returned.
Notes: None
11-4 OFF-LINE DIAGNOSTIC MANUAL