Version 3 Hardware System Board Diagnostics - AT&T 3B2 Off-Line Diagnostic Manual

Version 3 Hardware System Board Diagnostics
This section contains a description of the diagnostic phases and tests for the 3B2/500, 522, 600,
622, 700, and 1000 computer System Boards (SBOs). These phases and tests are applicable to UNIX
System V Release 3.2.1 and subsequent releases. Note that unlike Version 2 SBO diagnostics, the MAU
diagnostic tests are not included as part of the SBO diagnostic tests. The MAU diagnostics tests are
located in Chapter 12.
The SBO is a highly integrated circuit board that is the primary element of the 3B2 computer. The
following components are found on the SBO:
• MAU
• MMU
• Internal Cache (if present)
• WE 32100 or WE 32200 Multiprocessor
• Oynamic Random Access Memory (ORAM) Controller
• Interrupt Structure
• Timers (includes Time-of-Oay clock, Periodic timer, and Bus timer)
• Control and Status Register (CSR)
• Erasable Programmable Read Only Memory (EPROM)
• Nonvolatile Random Access Memory (NVRAM).
The following 22 phases check all aspects of the Version 3 computer SBOs except the MAU which
has a separate set of diagnostic phases. The MAU phases are found in Chapter 12. You can refer to the
Table of Contents in Chapter 12 for a summary of the SBO phases performed. The phases are
organized in the same order that they are run on the 3B2 computer.
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