Phase #10 Tests - AT&T 3B2 Off-Line Diagnostic Manual

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Phase' #10 - CPU Lower Chip Select Test
Phase Name:
Type:
Function:
Tests:
Time:
Warnings:
Notes:
Phase #10 Tests
NI CPU_S (cpu_S)
Demand
This phase tests the operation of the Lower Memory Chip Select (LMCS)
register of the INTEL 80186 CPU.
Tests 1 through 12 - check the LMCS register.
1 second
None
If any test in this phase fails, the following hardware may be faulty:
• INTEL 80186 Microprocessor
• INTEL 80186 Microprocessor interface to the NI Address/Data bus.
Test Numbers: 1 through 12
Function: These tests verify that the LMCS register is functional.
Procedure: A valid data pattern is written to the register and verified with a read.
Hardware Tested: The LMCS register is tested.
Data Returned: The test number that failed, the actual data, and the expected data are returned.
NETWORK INTERFACE DIAGNOSTICS 7-17