AT&T 3B2 Off-Line Diagnostic Manual page 122

Version 3 Hardware System Board Diagnostics - - - - - - - - - - - - - - - - - - - - -
Te~umber:
3
Function: This test verifies that dynamic memory is being refreshed by storing a data
pattern in memory, delaying 60 seconds, and confirming data retention.
Procedure: All of memory is cleared, followed by a delay of approximately 60 seconds.
Then each memory location is read and verified. This is repeated for an
alternate data pattern.
Hardware Tested: The Dynamic Memory is tested.
Data Returned: The failing address, the expected data, and the actual data are returned.
Notes: None
Test Numbers:
Function:
Procedure:
4 through 6
These tests check variable size accesses.
Tests 4 through 6 execute as follows:
Test 4 - checks by writing words and reading back as shorts. Increment
address by 1000.
Test 5 - checks by writing two shorts and reading back as bytes. Increment
address by 1000.
Test 6 - checks by writing and reading 4 bytes. Increment address by 1000.
Hardware Tested: The Dynamic Memory is tested.
Data Returned: The failing address, the expected data, and the actual data are returned.
Notes: None
Test Numbers:
Function:
Procedure:
7 through 16
These tests check that all single-bit errors can be detected and reported
correctly in the Hardware Fault registers and in the Control Status and Error
Register (CSER).
Walk a one through a field of zeros in bits D6 through DIS using the following
binary memory half words:
DIS D6 D5 DO (D5 through DO are Check bits)
0000000000 001111
When the error is forced, read the CSER confirming that the Single-bit Error bit
was set, that an interrupt was processed, and the correct syndrome bit/address
information was stored in the Hardware Fault registers.
Hardware Tested: The Dynamic Memory, CSER, and Hardware Fault registers are tested.
Data Returned: The failing address, the expected data, and the actual data are returned.
Notes: None
3-82 OFF-LINE DIAGNOSTIC MANUAL